Typical serial data communications systems, such as LAN and disk drive systems, use a single channel to send and receive data and clock information between two users. Embedding data and clock information into a single channel is typically done to minimize wiring or improve recording media data densities. A variety of different schemes, such as run length limited and manchester encoding, are used to embed the clock information into the data signal. These schemes strive to transfer data as efficiently as possible while minimizing the likelihood of improperly recovering the data. (Bit error rate: BER). Part of the task of recovering data at the receiving end of such a data link is to re-establish a local receive clock which frames (or denotes data bit) boundaries. Many of these schemes utilize both the rising and the falling (i.e. positive and negative) transitions of the channel information to denote data states and/or clock (also referred to as a data cell) boundaries.
Referring to FIG. 1, a data cell 200 in one of the above mentioned schemes is defined as the minimal allotted time during which a data signal 102 is allowed to transition or change state. During the data recovery process, the data signal 102 is sampled to determine the presence or the absence of a rising (positive) data transition 204 or a falling (negative) data transition 206. Under ideal conditions, the transitions 204, 206 occur in the center of the data cell 200. If a transition 204, 206 occurs within the data cell 200, the occurrence of the transition, either positive or negative, is represented as a logic high or "1"; if no transition has occurred, this situation is represented as a logic low or "0". For example, for the data signal 102 illustrated, the data signal 102 may be represented as "1101011" over the period of seven data cells 200. The type of data/clock encoding algorithm employed determines how these data cells are grouped to translate (encode/decode) between words of strictly data and data with embedded clocks. The particular encoding scheme employed may depend upon the required needs or characteristics of the media (i.e., magnetic media flux density dependent bit shift) or the constraints of the recovery system (i.e., desire for no DC averaged component in the information transmitted.). The chosen grouping of data patterns will be tailored to ease the task of correctly regenerating the local receive clock (i.e., minimize the probability that it frames the data at the wrong data rate). A harmonic lock condition is an example of where the data transition spacings deceive the local clock into running at a stable but incorrect frequency.
In the FDDI system, a 4B/5B RLL encoding scheme is employed. The required data rate is 100 Mbits/sec. Due to the 4 bit to 5 bit encoding, the frequency of the local receive clock is 125 MHz. Since 1/125 MHz=8 ns., each of the data cells 200 is 8 ns. wide. Hence, every 8 ns. the data signal 102 is sampled to determine whether the data signal 102 has changed states (i.e., transitioned). Ideally the data transitions 204, 206 would occur 4 ns. into the data cell 200. (I.e., in the center of the data cell 200). This centering allows for margin in the placement of any given transition during actual transmission due to degradations in the components in the data path (drivers, transmission media, sync noise).
Referring to FIG. 2, as previously discussed, typically a separate clock signal is not sent in conjunction with the data because it is expensive to dedicate a separate channel for the clock signal. Rather, the clock information is embedded into the data signal. The clock information is extracted from the data signal by running a local oscillator (or receive clock) at a multiple of the data signal's transition rate.
The local receive clock must, by nature, be capable of varying its frequency to align itself in phase and frequency to the incoming channel information. This frequency shift and phase alignment capability is typically accomplished using a phase lock loops (PLL). A conventional PLL system 10 employs a voltage controlled oscillator (VCO) 20 as the local clock source. The VCO's frequency is stabilized by comparing its rising phase transitions with the phase transitions of a reference signal 12. The reference signal 12 is input to a phase comparator 16 along with the VCO transition signal 28 which compares the phase of the two incoming signals 12, 28 and generates a correction signal 30 indicative of the difference between them. The correction signal 30 is active for and proportional to the time difference between the two signals 12, 28 and instructs the VCO 20 how much to speed up or slow down in order to properly track the interval rate of the reference signal 12. If the reference signal 12 arrives at the phase comparator 16 first, it has a higher frequency than the VCO transition signal 28 and the correction signal 30 instructs the VCO 20 to increase its voltage which, in turn, increases its frequency.
If the VCO 20 has a higher frequency (faster) than the frequency of the reference signal 12, then the VCO transition signal 28 arrives at the phase comparator 16 first and the correction signal 28 instructs the VCO 20 to decrease its frequency. The correction signal 30 is input to a low pass RC filter (LPF) 18. Hence, if the VCO 20 has a higher frequency than the reference signal 12, the correction signal 30 generated discharges the filter capacitor; conversely, if the VCO 20 has a lower frequency (slower) than the reference signal 12, then the capacitor is charged up increasing the voltage of the VCO 20 thereby increasing the frequency of the VCO transition signal 28.
If the phase of the incoming signals 12, 28 are aligned, then the phase comparator 16 does not output a correction signal 30; if the phase of the two signals 12, 28 are not aligned, then the phase comparator 16 does output a correction signal 30. As the phases of the two input signals 12, 28 become closer together, the correction pulse 30 gets narrower. The two signals 12, 28 need not have the same duty cycle. In most PLL phase comparator circuits, the correction signal 30 is the summation of a pump up and a pump down current pulse generator. It is a common practice in these systems, that in order to deal effectively with the case of close phase alignment to ensure that the pump up and the pump down components always have some finite minimum pulse width which is not zero (to avoid introducing deadband effects.) If the phase comparator circuit does not output a correction signal this implies that the summation of the pump up and the pump down components equals about zero (although they each may have some minimum complimentary magnitude pulse width).
While the conventional PLL system 10 is able to generate a system clock signal from the reference signal 12 it receives, there are several disadvantages associated with using the conventional PLL system 10 as a clock recovery system.
In a conventional PLL system the reference signal transitions that are tracked occur at a continuous rate, where in a serial data system the data transitions, which serve as the reference signal being tracked, occur at irregular but precisely spaced intervals due to the data content. Consequently, in a serial data system it is necessary to recognize when a data transition is not going to occur at the next anticipated interval and to gate off the VCO transition signal from being presented to the phase comparator 16.
In the conventional PLL system, the phase comparator 16 makes a phase comparison regardless of whether a phase transition 204, 206 has occurred in the data signal 12. In a serial data application, a serial data signal 12 is used as the referenced signal. In a serial data clock recovery system a phase comparison need only be made if a data transition has occurred. If the data signal 12 does not have a transition 204, 206 during a particular clock cycle, then it is assumed that the VCO 20 is operating at the proper frequency.
Failure to gate off the VCO transition signal 28 from being detected when no data transition is anticipated causes the PLL 10 to think that the data is merely late (or conversely, that the VCO frequency is incorrectly running too fast.) As such, the PLL 10 will attempt to correct the VCO's frequency when a correction comparison is not appropriate (since no transition occurred for a comparison to be made).
In order to gate off the VCO transition signal 28, in anticipation of a data transition not occurring, the data information presented to the reference input of the phase comparator 16 may be delayed. Another modification necessary to adapt the conventional PLL for serial data application is to make both rising and falling phase comparisons of the reference (data) signal.
Referring to FIG. 2b, a conventional clock recovery system 400 is illustrated, wherein elements similar to those in other figures are given the same name/reference numerals. The conventional system 400 incorporates the above mentioned modifications to a conventional PLL 10 by including a VCO gating and data transition detection element 312, and a delay line 22. The system's 400 performance can be degraded if the delay line 22 is not capable of passing the data pulses if the pulses become too narrow. In addition, the system's performance can be degraded if the delay of rising 204 or falling 206 transitions through the delay line 22 are not matched. As the conventional system 400 tracks the average position of the transitions, errors in the matching of rising and falling transition delays reduce the amount available that a given data transition can be displaced, from a nominal amount (window margin), before it is not detected as occurring within that window.
This invention addresses these issues and provides a clock recovery system for use in data transmission network: the Fiber Distributed Data Interface (FDDI), a large protocol concentrator design (back plane data distribution). The Fiber Distributed Data Interface (FDDI) protocol is an American National Standards Institute (ANSI) data transmission standard which applies to a 100 megabit/second token ring network that utilizes an optical fiber transmission medium. The FDDI protocol is described in "FDDI-An Overview," Digests of Papers IEEE Computer Society Int'l Conf., Compcon '87, Jan, 1987, which is herein incorporated by reference. The FDDI protocol was intended as a high performance interconnection among mainframe computers as well as among mainframes and their associated mass storage sub-systems and other peripheral equipment.